V. Pogoretskiy, J.P. van Engelen, J.J.G.M. van der Tol and Y. Jiao
in the Proceedings of the 23nd Annual Symposium of the IEEE Photonics Society Benelux Chapter, 15-16 November 2018, Vrije Universiteit Brussel, Brussel, Belgium.
Publication year: 2018


In this work we present a technique of wafer scale bonding of photonic integrated circuits to a silicon carrier, which enables flexible design of active and passive photonic integrated devices. Exploiting this bonding technique we can use double side processing of the photonic membrane, avoid planarization steps and achieve high index contrast in the waveguides, which supports the design of complex systems with small footprint.

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